1. Field of the Invention
The present invention relates, in general, to a semiconductor package and method for fabricating the same and, more particularly, to a semiconductor package and method for fabricating the same that allows a plurality of semiconductor chips to be fixedly stacked in a single, thin package.
2. Description of the Prior Art
Currently, there is a tendency in which a plurality of semiconductor chips are packaged and mounted on the motherboard of an electronic device such as a PCS phone, a cellular phone or a notebook to perform various functions within a minimum time, and semiconductor packages in which semiconductor chips are packaged and the electronic devices on which the semiconductor packages are mounted are miniaturized. In the meantime, in order to allow a semiconductor package to be thinned, there has been fabricated a semiconductor package in which an opening is formed in a circuit board and a semiconductor is disposed in the opening.
With reference to FIG. 7, the construction of such a semiconductor package 100′ is described as follows.
As depicted in the drawing, reference numeral 20′ designates a circuit board 20′ that has an opening 27′. A semiconductor 2′ on the upper surface of which a plurality of input/output pads 4′ are formed is disposed in the opening 27′ of the circuit board 20′. The circuit board 20′ comprises a base resin layer 21′. A circuit pattern including a plurality of bond fingers 22′ and ball lands 23′ are formed on the upper surface of the base resin layer 21′. The surface of the circuit pattern is coated with a cover coat 24′ with the bond fingers 22′ and the ball lands 23′ being exposed upward out of the cover coat 24′. The input/output pad 4′ of the semiconductor chip 2′ is electrically connected to the bond fingers 22′ of the circuit board 20′ by means of connection means 30′. Additionally, an encapsulation 40′ is formed around the semiconductor chip 2′ and the connection means 30′ so as to protect them from the external environment. A plurality of conductive balls 50′ are respectively fusion-welded on the ball lands 23′ to allow the package to be easily mounted on a motherboard.
However, in the conventional semiconductor package 100′, since only a single semiconductor chip 2′ is disposed in the opening 27′, there is an inherent shortcoming in the high density, function and capacity of semiconductor package 100′.
Furthermore, in a case where the semiconductor chip 2′ disposed in the opening of the circuit board 20′ is a memory chip, such as a flash memory chip, SRAM chip or the like, since a plurality of semiconductor packages 100′ must be mounted on a motherboard (not shown), there occurs a problem in which the mounting density is limited.
Recently, there is an increased desire for a semiconductor in which an ASIC (application specific integrated circuit) semiconductor chip and a memory semiconductor chip are packaged together. However, the desire is not satisfied by the conventional semiconductor package.
In order to overcome the problem, there has been developed a stack type semiconductor package in which a plurality of semiconductors respectively having various functions are packaged into a single semiconductor package by stacking the semiconductor chips together. The construction of the stack type semiconductor package is depicted in FIGS. 8A and 8B. FIG. 8A is a cross section of the package. FIG. 8B is a plan view showing the package in a state where the package is not coated with an encapsulation.
In the conventional stack type semiconductor package, a circuit board 10 on which bond fingers 12 are formed includes a resin layer 11, circuit patterns 19 are formed on the upper and lower surfaces of the resin layer 11, and a first semiconductor chip 1 is bonded on the center portion of the circuit board 10 with a bonding layer 7 interposed between the circuit board 10 and the first semiconductor chip 1. Reference numeral 14 designates conductive via holes for connecting the upper circuit pattern 18 to the lower circuit pattern 18, and reference numeral 15 designates cover coats for protecting the circuit patterns 19 from the external environment.
In addition, a second semiconductor chip 2 is bonded on the upper surface of the first semiconductor chip 1 with a bonding layer 7 interposed between the first and second semiconductor chip 1 and 2. The input/output pads 4A of the first semiconductor chip 1 and the input/output pads 4A of the second semiconductor chip 2 are formed along rectangular directions to prevent them from being overlapped. That is, as illustrated in FIG. 8B, the input/output pads 4A of the first semiconductor chip 1 and the input/output pads 4A of the second semiconductor chip 2 are prevented from being overlapped, in such a way that the input/output pads 4A of the first semiconductor chip 1 are arranged along the front and rear edges of the first semiconductor chip 1 and the input/output pads 4A of the second semiconductor chip 2 are arranged along the side edges of the second semiconductor chip 2. The input/output pads 4A of the first semiconductor chip 1 and the second semiconductor chip 2 are respectively connected to the bond fingers 12 of the circuit board 10 by means of connection means 20, such as conductive wires. A plurality of conductive balls 40 are respectively fusion-welded on a plurality of ball lands 13, which are formed on the lower surface of the circuit board 10, to transmit signals to a mother board. In the meantime, the first semiconductor chip 1, the second semiconductor chip 2 and the connection means 20 are encapsulated with an encapsulation 30 to protect them from the external environment.
However, in the conventional stack type semiconductor package 101′, the first semiconductor chip is bonded on the circuit board and the second semiconductor chip is bonded on the first semiconductor chip. Accordingly, the package is very thick which is contrary to recent trends.
Additionally, since the height difference between the input/output pads and the circuit board is excessively enlarged, the loop height of the connection means, such as conductive wires that connect the second semiconductor chip to the circuit pattern, tends to be enlarged. Accordingly, since the loop angle becomes an acute angle, the sweeping phenomenon of the conductive wires occurs easily by the filling pressure during a molding process, thereby causing the inferiority of the package.
As another example of the conventional semiconductor package, a composite stack type semiconductor package 102′ is illustrated in FIG. 9.
As depicted in the drawing, the conventional composite stack type semiconductor package is fabricated by stacking a plurality of conventional Ball Grid Array (BGA) semiconductor packages.
In each of the BGA semiconductor packages, a semiconductor chip 1 is positioned in the opening of a circuit board 10 on the upper and lower surfaces of which ball lands 13 are formed, the input/output pads (not shown) of the semiconductor chip 1 are respectively connected to the bond fingers 12 of conductive material formed on the upper surface of the circuit board 10 by conductive wires 20, the ball lands 13 are electrically connected to the bond fingers 12 through conductive via holes 14, conductive balls 40 are fusion-welded on the ball lands 13, and an encapsulation 30 is formed on the upper surface of the circuit board 10 to protect the semiconductor chip 1 and the conductive wires 20 from the external environment. In this case, the bond fingers 12 formed on the upper surface of the circuit board 10 are exposed to the outside, and projected pads 8 are respectively formed on the bond fingers 12.
In this conventional BGA package, since the semiconductor chip is disposed in the opening in the central portion of the circuit board, the semiconductor package can be fabricated to be relatively thin. Additionally, a plurality of BGA packages are stacked in such a way that one BGA package is bonded on another BGA package with the solder balls on the lower surface of the upper BGA being fusion-welded on the projected pads on the upper surface of the lower BGA, thereby increasing the mounting density of the package.
However, in the conventional composite stack type semiconductor package 102′, since projected pads are formed on the periphery of the circuit board of the BGA package 103′ and solder balls are fusion-welded on the projected pads, the semiconductor package causes inconvenience in having an extra step to form the projected pads, and has a limitation on the reduction of the thickness of electronic devices owing to the thickness of the projected pads. Additionally, in each of BGA packages, since a single chip is mounted in each package, there occur limitations on the maximization of the memory capacity of each package and the increase of the mounting density of each package.